Author: Siamak Arya

Publication Overview

Publication period start: 1995

Number of co-authors: 2

Co-Authors

Number of publications with favourite co-authors

Howard Sachs

Sreeram Duvvuru

Productive Colleagues

Most productive colleagues in number of publications

Howard Sachs

Sreeram Duvvuru

Publications

Arya, Siamak, Sachs, Howard, Duvvuru, Sreeram (1995): An architecture for high instruction level parallelism. In: HICSS 1995 , 1995, . pp. 153-162. https://csdl.computer.org/comp/proceedings/hicss/1995/6930/00/69300153abs.htm

Duvvuru, Sreeram, Arya, Siamak (1995): Evaluation of a branch target address cache. In: HICSS 1995 , 1995, . pp. 173-180. https://csdl.computer.org/comp/proceedings/hicss/1995/6930/00/69300173abs.htm